instruction decoder

См. также в других словарях:

• instruction decoder — komandų dekoderis statusas T sritis automatika atitikmenys: angl. command decoder; instruction decoder vok. Befehlsdecodierer, m; Befehlsentschlüßler, m rus. дешифратор команд, m pranc. décodeur d instruction, m …   Automatikos terminų žodynas

• Decoder — For the drum and bass musician, see Decoder (artist). For the band, see Decoder (band) A Digitrax DH163AT DCC decoder in an Athearn locomotive before the shell goes on. A decoder is a device which does the reverse operation of an encoder, undoing …   Wikipedia

• decoder — [dē kōd′ər, dē′ kōd′ər] n. 1. a person who decodes messages 2. a device that decodes scrambled messages sent by telephone 3. in an electronic digital computer, a circuit device that determines the content of a given instruction or performs… …   English World dictionary

• Instruction cycle — An instruction cycle (sometimes called fetch and execute cycle, fetch decode execute cycle, or FDX) is the basic operation cycle of a computer. It is the process by which a computer retrieves a program instruction from its memory, determines what …   Wikipedia

• command decoder — komandų dekoderis statusas T sritis automatika atitikmenys: angl. command decoder; instruction decoder vok. Befehlsdecodierer, m; Befehlsentschlüßler, m rus. дешифратор команд, m pranc. décodeur d instruction, m …   Automatikos terminų žodynas

• décodeur d'instruction — komandų dekoderis statusas T sritis automatika atitikmenys: angl. command decoder; instruction decoder vok. Befehlsdecodierer, m; Befehlsentschlüßler, m rus. дешифратор команд, m pranc. décodeur d instruction, m …   Automatikos terminų žodynas

• No instruction set computing — (NISC) is a computing architecture and compiler technology for designing highly efficient custom processors and hardware accelerators by allowing a compiler to have low level control of hardware resources. Contents 1 Overview 2 History 3 See also …   Wikipedia

• Trace vector decoder — is a system that uses a microprocessor s trace mode to decode encrypted code just in time before it is executed and possibly re encrypt it after the execution. It can be used to enforce copy protections for some computer systems.Trace Vector in… …   Wikipedia

• Sum addressed decoder — In CPU design, a Sum Addressed Decoder or Sum Addressed Memory (SAM) Decoder is a method of reducing the latency of the CPU cache access. This is achieved by fusing the address generation sum operation with the decode operation in the cache… …   Wikipedia

• Viterbi decoder — A Viterbi decoder uses the Viterbi algorithm for decoding a bitstream that has been encoded using forward error correction based on a convolutional code. There are other algorithms for decoding a convolutionally encoded stream (for example, the… …   Wikipedia

• IBM POWER — POWER is a RISC instruction set architecture designed by IBM. The name is a backronym for Performance Optimization With Enhanced RISC . POWER is also the name of a series of microprocessors that implement the instruction set architecture (ISA).… …   Wikipedia